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IRS20955(S)PbF
where
Power Supply Decoupling
As the IRS20955S contains analog circuitry, careful
attention must be given to decoupling the power
supplies for proper operation. Ceramic capacitors of
0.1 μF or more should be placed close to the power
supply pins of the IC on the board.
Please refer to the application note AN-978 for
general design considerations of a high voltage gate
driver IC.
V SS Negative Bias Clamping
V SS can go below COM when a negative supply is
missing in a dual supply configuration. In this case,
excessive negative V SS voltage with respect to COM
could damage the IRS20955S. Having a diode to
clamp potential negative biases to V SS is
recommended to protect the IC. A standard
recovery diode with a current rating of 1 A such as
the 1N4002 is sufficient for this purpose.
P ZDD = the power dissipation from the internal
Zener diode clamping V DD
P LDD = the power dissipation from the internal
logic circuitry
V +BUS = the positive bus voltage feeding V DD
R DD = the resistor feeding V DD from V +BUS
*For obtaining the value of R DD , refer to the
section “Supplying V DD .”
2. P LSM : Power Dissipation of the Input
Level Shifter
P LSM = 2 nC x f sw x V SS,BIAS
where
f SW = the PWM switching frequency
VDD
CSD
IN
VSS
NC
VREF
CSH
VB
HO
VS
NC
VCC
V SS,BIAS = the bias voltage of V SS with respect to
COM
3. P LOW : Power Dissipation in Low-Side
Negative VSS
Clamping Diode
OCSET
DT
LO
COM
The power dissipation in low-side comes from
the losses of the logic circuitry and the losses of
= ( I QCC ? V CC ) + ? Vcc ? Q g ? f SW ?
? ?
?
R O + R g + R g (int) ? ?
?
-Vbus
Figure 21. Negative V SS Clamping
Junction Temperature Estimation
The power dissipation in the IRS20955S is
dominated by the following items:
- P MID : Power dissipation of the floating input
logic and protection circuitry
- P LSM : Power dissipation of the input level
shifter
- P LOW : Power dissipation in low-side
- P LSH : Power dissipation of the high-side
level shifter
- P HIGH : Power dissipation in high-side
1. P MID : Power Dissipation of the Floating
Input Logic and Protection Circuitry
The power dissipation of the floating input
driving LO.
P LOW = P LDD + P LO
R O
?
where
P LDD = the power dissipation from the internal logic
circuitry
P LO = the power dissipation from the gate drive
stage to LO
R O = the output impedance of LO, typically 10 ? for
the IRS20955S
R g(int) = the internal gate resistance of the low side
MOSFET driver, typically 10 ? for the IRS20955S
R g = the external gate resistance of the low side
MOSFET
section is given by:
P MID = P ZDD + P LDD ≈
www.irf.com
V + BUS ? V DD
R DD
? V DD
Q g = total gate charge of the low side MOSFET
17
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